1. Field of the Invention
The present invention relates to techniques for verifying an integrated circuit design. More specifically, the present invention relates to a method and apparatus for verifying a simulated wafer image against an intended design.
2. Related Art
As feature sizes on integrated circuit (IC) chips become smaller than the wavelength of light used to expose the features on the wafer, optical proximity correction (OPC) and other resolution enhancement techniques (RET) are being used to ensure that the mask patterns produce the intended design on the wafer. As RET techniques become more aggressive, the task of verifying the accuracy of the final pattern on the wafer becomes too complex for simple Design Rule Checking (DRC) techniques. Instead, Lithography Rule Checking (LRC) techniques are used to physically verify complex RET mask patterns. LRC techniques use model-based simulations of the mask patterns to produce a simulated physical layout of the structures fabricated on the wafer. The simulated physical structures are then compared against the intended design (i.e., target pattern).
For example, one LRC technique uses MERGE_TOP flow in the Synopsys SiVL® product. (Synopsys SiVL is a registered trademark of Synopsys, Inc. of Mountain View, Calif.) In MERGE_TOP flow, the target pattern data (i.e., pre-OPC data) and the mask pattern data (i.e., post-OPC data) are merged into a single hierarchy in which one branch is the full pre-OPC data and the other branch is the full post-OPC data. A single top cell is created, which is the parent of the top cell of the pre-OPC data and the top cell of the post-OPC data. The data in both the target pattern and the mask pattern are then fed into the SiVL flow and are traversed serially to partition the hierarchical layout of the full chip into multiple sub-sections, called “templates.” A template is a cell placement with unique context within the environment of the cell placement. The templates are then distributed across multiple computing nodes in a distributed processing environment to perform model-based simulations on the post-OPC mask patterns in parallel. The pre-OPC layout provided by designers is then compared against the model-based simulations of the post-OPC layout to determine if the post-OPC layout produces the intended design.
Unfortunately, the serial process involved in data partitioning is extremely time-consuming and limits the performance of the whole verification flow. Hence, what is needed is a method and an apparatus for verifying a simulated wafer image against an intended design without these performance problems.